1. Field of the Invention
This invention relates generally to a semiconductor DRAM memory cell and more specifically to a method for making a semiconductor DRAM memory cell with an N type conductivity capacitance implant region self-aligned with the gate of the access transistor.
2. Description of the Prior Art
FIG. 1 illustrates a high-capacity dynamic random access memory (DRAM) cell structure. The high-capacity DRAM cell structure 50 has two double level polysilicon cells 20.sub.1, 20.sub.2, each of which includes an access transistor 21 and a storage capacitor 22. In the figures, a single number without a subscript refers to like features in each of cells 20.sub.1, 20.sub.2 since the cells generally have mirror symmetry about the center of source region 13. For example, cell 20 refers to both cells 20.sub.1 and 20.sub.2.
DRAM cell 20 has a pocket 13 of N+ conductivity type formed in a P- conductivity type (P- type) semiconductor substrate 10. Pocket 13, which is part of a diffused bit line, functions as the source for access 21 transistor in both cell 20.sub.1 and cell 20.sub.2.
A deep P-type conductivity implant region 11, typically a boron implant, and a shallow N-type conductivity implant region 12, typically an arsenic implant, are each formed a selected distance from the edge of source region 13. The distance from the edge of source region 13 to edge Y of N-type conductivity implant 12 is the channel length of access transistor 21. P implant isolation region 14, a channel stop region, and field oxide region 15 are formed on the periphery of DRAM cell 50. A thin oxide layer 18 overlies implant regions 11, 12, and field oxide region 15. Thin gate oxide layer 27 overlies source region 13 and the channel region. A first polysilicon layer 16 is formed on oxide layer 18 over field oxide 15 and arsenic implant region 12 and boron implant region 11. First polysilicon layer 16 functions as a storage gate for capacitor 22 of cell 20. A transfer gate 19 is a second polysilicon electrode that is separated from the first polysilicon electrode by a silicon dioxide layer 17 and from the channel region and source 13 by silicon dioxide layer 27.
The double level polysilicon DRAM memory cell, as illustrated in FIG. 1, is widely used in DRAM arrays because the cell size is significantly reduced over other conventional charge storage DRAM cells. The charge from bit line 13 is transmitted directly to the area under storage gate 16 by the connection of inversion layers under the transfer gate 19 and storage gate 16.
The threshold voltage of transistor 21 is a function of the effective channel length and the coupling of capacitance arsenic region 12 to its polysilicon transfer gate 19. Therefore, variations introduced in either the effective channel length or the coupling of capacitance region 12 and transfer gate 19 by fabrication processes reduce yield because the process variations change the coupling in cells 20.sub.1, 20.sub.2 which in turn results in different threshold voltages for cells 20.sub.1, 20.sub.2.
The cells 20.sub.1 and 20.sub.2 (FIG. 1) are fabricated on a semiconductor chip having many thousands of similar cells and successful operation of the chip requires that all such cells on the chip be free of defects. The cells as shown are fabricated using conventional oxidation, masking, etching and ion implantation which are known to those skilled in the art. In fabrication of cell 20, positioning of edge Y of capacitance arsenic ion implant 12 with respect to the positioning of respective gate edge X is critical, because for proper operation of cell 50, raising the gate 19 voltage must access the information in the associated capacitor 22.
Thus, variations introduced by fabrication processes, discussed above, can directly affect the proper operation of cell 50. For example, edge Y.sub.1 of capacitance arsenic ion implant region 12.sub.1 and the edge Y.sub.2 of implant region 12.sub.2 are formed in the same process step. Specifically, an ion implant mask is used to define regions 12.sub.1, 12.sub.2. If the mask is misaligned, an acceptable positioning of one edge of the implant region 12 may lead to an unacceptable positioning of the other edge. The cell having acceptably aligned edges would function while the adjacent cell, having an unacceptably aligned edge of implant region 12, would not function. Therefore, yield is reduced by this alignment problem. The complexity of having a second level of polysilicon in the DRAM cell adds significantly to the processing cost. Accordingly, the mask misalignment and similar variations, which result in reduced yields, limit the advantages of the reduced cell size of the double level polysilicon approach.